Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, One. Drive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the DFX (Design for Test & Debug) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Design for Test (DFT) Engineer to join the team. Responsibilities. Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products. Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these I - Ps, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic. Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI. Provide test plans and engage closely with verification engineers to perform waveform reviews. Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage. Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis. Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies. Qualifications. Required Qualifications:Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1 year(s) technical engineering experience. OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4 years technical engineering experience. OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5 years technical engineering experience. OR equivalent experience. 4 years of experience in the field of DFT knowledge about industry standard practice in Design for Test. ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time. Other Requirements:Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications:Experience with Test Chip development and some unique challenges it brings about for DFT. Experience developing Scan architecture & micro-arch specifications as it relates to large SO - Cs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits. Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys Test. Max. Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools. Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage. Experience with Static Timing Analysis & constraint generation. Experience with ATE and Silicon bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis. Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable. Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency. Confident problem solver who thrives under pressure to find new, creative solutions. #SCHIE #CSME Silicon Engineering IC 4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

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